1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same.
Priority is claimed on Japanese Patent Application No. 2010-033673, Feb. 18, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, as semiconductor devices have been shrunken, short channel effects have been serious where the length of a channel of a transistor is shorter than a predetermined length, for example, a length that allows transistors to perform stable operations. Such short channel effects make it difficult for the semiconductor devices to stably and normally operate.
To solve this problem, there is a proposal for a semiconductor device in which a vertical transistor is used, which includes a pillar. The pillar can be formed by processing the surface of a semiconductor substrate. This is disclosed in Japanese Unexamined Patent Application, First Publication, No. JP-A-2009-081377.
In the semiconductor device disclosed in Japanese Unexamined Patent Application, First Publication, No. JP-A-2009-081377, a plurality of pillars are disposed at varying intervals over the semiconductor substrate. The intervals vary in transverse and longitudinal directions in plan view. The semiconductor device includes word lines. The word line includes gate electrodes. The word line extends to contact with the plurality of pillars. Further, a plurality of crossing trenches are formed for forming the plurality of pillars defined by the plurality of crossing trenches. An insulating layer fills the plurality of crossing trenches.